(a) Field of the Invention
The present invention relates to a built-in self test (BIST) circuit, and more particularly, to a BIST circuit which is capable of generating a test pattern including series of test input signals and test result signals.
(b) Description of the Related Art
A BIST circuit is incorporated in an LSI for testing the function of the LSI. The LSI is evaluated by the BIST circuit as to non-defectiveness in the function thereof after the completion of the product. FIG. 10 shows a conventional BIST circuit incorporated in a system LSI (logic circuit), described in Patent Publication JP-A-8-15382.
A plurality of scan paths 62 are formed each grouping the flip-flops disposed in the internal circuit of the LSI 61, when a test mode is selected for the LSI. Each scan path 62 connects the group of flip-flops in a cascade (serial) connection, and is associated with a corresponding scan-in pin 65 which receives a series of input scan-in signals, i.e., scan-in signal pattern. The received scan-in signal pattern is shifted forward along the scan path 62 through the flip-flops, which operate with a clock signal, to be output from the scan path 62.
Each scan-in signal passed by the scan path 62 is delivered to a corresponding logic gate 66, and compared by using a logic operation in the logic gate 66 against the scan-in signal which is directly input to the logic gate 66. The comparison results are delivered to the data compression unit 64 from the logic gates 66. In the logic operation for the comparison, an external pin 67 is used for receiving a specified signal, which masks some signals liable to assuming unstable states of logic after passing the scan path. The data output from the data compression unit 64 is delivered to an external LSI tester through the scan-out pins (not shown). By examining the data from the data compression unit 64, presence or absence of a defect in the internal circuit of the LSI can be judged. The circuit test using the above scan paths costs a large amount of time due to the configuration wherein the serially connected flip-flops consecutively shift the scan-in signal responding to the clock signal.
The BIST circuit is also used for examining the non-defectiveness of memory cells in a semiconductor memory device such as a DRAM. In the evaluation of memory cells, a variety of test patterns including a marching pattern and a checkered pattern are generally used. The BIST circuit includes a test pattern generator block for generating test patterns including a series of data patterns and a variety of address patterns, the latter specifying the memory cells from the first address to the final address. The BIST circuit writes and reads data “1” or “0” specified by the data pattern into/from memory cells of the addresses specified by the address pattern, and compares the read data against the preceding write data to examine the non-defectiveness of the memory cells and corresponding interconnects. The BIST circuit incorporated in the DRAM generally includes a test pattern generator block having a larger circuit scale due to the large number of test patterns being needed for examining the function of the DRAM.
Patent Publication JP-A-2000-76894 describes a BIST circuit having a test pattern generator, which generates another test pattern while using a counter, after a test using a previous test pattern is finished. This BIST circuit can generate a large number of test patterns by using a single pattern generator while suppressing the increase of the circuit scale.
As understood from the above description, the BIST circuits are designed for testing the presence or absence of defects in the LSIs after the fabrication processes thereof, the LSIs including a logic circuit and/or memory device. It is to be noted that the BIST circuit should also be designed correctly for achieving the function thereof because the BIST circuit itself is also one of the electric circuits in the LSI. The functions of the LSI including the BIST circuit are verified or examined based on the operations and the test results by the BIST circuit generating the test pattern during the test operation.
It is effective to verify the correctness of the circuits in the LSI by examining the interconnects therein during the design stage thereof for achieving reduction of costs and turn around time of the LSI by preventing defects from occurring in the next stages. In such a case, the verification must be achieved in both the internal circuit and the BIST circuit of the LSI. It is noted, for the design verification of the interconnects in the circuit, the test patterns generated by the test pattern generator in the BIST circuit may be effectively used.
However, since the ordinary test patterns generated by the test pattern generator are dedicated to finding the physical defects in the LSI, the number of test patterns is large. Thus, if the ordinary test patterns are used for verifying the LSI in the design stage thereof, the verification necessitates a larger amount of test time. In addition, if the verification test patterns for use in the design verification are manually created separately from the ordinary test patterns to be generated by the BIST circuit, this costs huge man-hours to thereby raise the fabrication costs of the LSI.
In view of the above, it is an object of the present invention to provide a BIST circuit capable of facilitating the design verification of an LSI including the BIST circuit which generates test patterns for testing the internal circuit of the LSI.
It is another object of the present invention to provide a method for verifying the design of an LSI including a BIST circuit by using the test patterns to be generated by the BIST circuit itself.
The present invention provides a built-in self test (BIST) circuit for testing an internal circuit of an LSI, including a verification test pattern generator for generating a verification test pattern, wherein the verification test pattern is dedicated to verification of electric connections in the LSI.
The present invention also provides a method for testing the LSI by using the BIST circuit according to the present invention.
In accordance with the BIST circuit and the method of the present invention, since the test patterns to be generated by the verification test pattern generator in the BIST circuit are used for verification of design connections in the LSI during the design stage thereof, man-hours for creating the verification test patterns can be reduced. In addition, since the number of test patterns to be generated by the verification test pattern generator can be much smaller than the number of test patterns to be generated by the conventional test pattern generator due to the limited usage thereof, the time length needed to verify the design connections in the LSI can be reasonably short.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.